1. Technical Field
This disclosure relates to semiconductor testing, and more particularly, to a method for increasing test throughput by providing a method for determining bad handler sockets to avoid retest caused by bad socket performance.
2. Description of the Related Art
Fabricated semiconductor chips are tested to ensure quality and performance. Chip test systems include handlers and test heads, which provide a plurality of test sockets. Each test socket, in turn, includes a plurality of test pins. Many chips are tested in parallel, and each socket is employed to test one chip at a time. During testing operations, bad sockets go undetected, and are responsible for the rejection of otherwise good chips. At the end of a testing sequence or at a regular interval, sockets are recalibrated or tested to determine their status. Only then are the bad sockets determined. At this point all chips tested by these sockets must be retested. This results in reduced throughput and wasted time due to retesting.
Therefore, a need exists for a bad socket masking method, which identifies bad sockets during testing operations, and removes the bad sockets to prevent the bad sockets from continuing to test chips.
A method for testing semiconductor chips, in accordance with the present invention, includes connecting semiconductor chips to a plurality of sockets for testing the semiconductor chips. The sockets are contacted to perform testing on the semiconductor chips. The performance of the sockets are checked after a predetermined number of contacting steps by calculating a level of confidence for each socket. Sockets with the level of confidence exceeding a threshold level are masked during testing to prevent further testing with those sockets.
Another method for testing semiconductor chips in a lot, in accordance with the present invention, includes loading a portion of the lot of semiconductor chips into sockets of a handler of a tester for testing the semiconductor chips and contacting the sockets to perform testing on the semiconductor chips. The steps of loading and contacting are performed a predetermined number of times. The performance of the sockets are checked after the predetermined number of contacting steps by calculating a level of confidence for each socket. Sockets with the level of confidence exceeding a threshold level are masked to prevent further testing with those sockets for the rest of the lot of the semiconductor chips. The above steps are repeated until all of the semiconductor chips of the lot are tested.
In other methods, calculating a level of confidence for each socket may include calculating a level of confidence based on a cumulative probability function, and the cumulative probability function may include a binomial distribution. The step of contacting the sockets may include the step of performing a probe touchdown on the sockets to test the chips loaded in the sockets. The step of repeating the steps of contacting, checking and masking until all of the semiconductor chips in a lot are tested is preferably included. The sockets that have a level of confidence exceeding a threshold level are considered bad sockets, and the step of retesting only the chips tested by bad sockets which were determined to be bad sockets between a last step of checking the sockets and a current step of checking the sockets is preferably included. The step of masking may include the step of disabling the sockets with the level of confidence exceeding the threshold level by electrically disconnecting the sockets during testing or by reprogramming an operating system of the tester.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.